I've implemented a first version of a 6502 core. It has a very simple
architecture: First the command is read and then for every command a list
of microcodes are executed, controlled by a state machine. To avoid the
redundant VHDL typing, the VHDL code is generated with a Lisp program:
http://www.frank-buss.de/vhdl/cpu.lisp
This is the output:
http://www.frank-buss.de/vhdl/t_rex_test.vhdl
I've tested some instructions, like LDA, and looks like it works, but I'm
sure there are many bugs and not all features are implemented (e.g. BCD
mode or interrupt handling). It uses 2,960 LEs with Quartus 7.1, which is
too much compared to the 797 LEs of the T65 project. Any ideas how to
improve it? My idea was, that the synthesizer would be able to merge the
addressing mode implementations for the commands, but maybe this has to be
refactored by hand.
My goal is to beat the T65 project in LE usage. Speed and 100%
compatibility with the original 6502 (e.g. the strange S0 and V-flag
feature or the original hardware reset vectors) is not important for me,
but code compiled with http://www.cc65.org/ must work.
Most FPGAs have some kbyte memory (>5 kByte, even for inexpensive FPGAs,
freely configurable as ROM and RAM), so maybe a good idea would be to store
some microcode in memory? What instruction set is useful to implement the
6502 instruction set? Maybe a Forth-like microcode?
Any ideas how to improve the Lisp code? I like my idea of using a lambda
function in addressing-commands, because this looks more clean than a
macro, which I've tried first, but I don't like the explicit call of
emit-lines. How can I refactor it to a more DSL like approach?
--
Frank Buss, ··@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Frank Buss <··@frank-buss.de> writes:
> I've implemented a first version of a 6502 core. It has a very simple
> architecture: First the command is read and then for every command a list
> of microcodes are executed, controlled by a state machine. To avoid the
> redundant VHDL typing, the VHDL code is generated with a Lisp program:
>
[...]
>
> Any ideas how to improve the Lisp code? I like my idea of using a lambda
> function in addressing-commands, because this looks more clean than a
> macro, which I've tried first, but I don't like the explicit call of
> emit-lines. How can I refactor it to a more DSL like approach?
(Followup was set to comp.arch.fpga, but since this is Lisp-related,
I've changed followup to c.l.l.)
It seems to me that a more natural way to represent this code in a
Lisp program would be to use some form of syntax trees.
For example, the VHDL statement
if q = x"00" then z_flag <= '1'; else z_flag <= '0'; end if;
could be represented with this tree:
(if (= q #x00)
(<= z_flag #\1)
(<= z_flag #\0))
Producing VHDL code from the tree representation should be
straight-forward.
Peter Seibel's book has a chapter on HTML-generation which might be
helpful. You might also want to look up "abstract syntax" or "syntax
trees" in any compiler textbook.
Sven-Olof Nystr|m
Sven-Olof Nystr|m wrote:
> It seems to me that a more natural way to represent this code in a
> Lisp program would be to use some form of syntax trees.
>
> For example, the VHDL statement
>
> if q = x"00" then z_flag <= '1'; else z_flag <= '0'; end if;
>
> could be represented with this tree:
>
> (if (= q #x00)
> (<= z_flag #\1)
> (<= z_flag #\0))
>
>
> Producing VHDL code from the tree representation should be
> straight-forward.
Thanks, this is a good beginning. But my hope was something more abstract,
e.g. like Esterel:
http://www-sop.inria.fr/esterel.org/home.htm
but in Lisp. My idea is to write algorithms in a more natural way than with
state machines and then it will be compiled into VHDL (even better would be
into EDIF netlists).
--
Frank Buss, ··@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Frank Buss <··@frank-buss.de> writes:
> > For example, the VHDL statement
> >
> > if q = x"00" then z_flag <= '1'; else z_flag <= '0'; end if;
> >
> > could be represented with this tree:
> >
> > (if (= q #x00)
> > (<= z_flag #\1)
> > (<= z_flag #\0))
> >
> >
> > Producing VHDL code from the tree representation should be
> > straight-forward.
>
> Thanks, this is a good beginning. But my hope was something more abstract,
> e.g. like Esterel:
>
> http://www-sop.inria.fr/esterel.org/home.htm
>
> but in Lisp. My idea is to write algorithms in a more natural way than with
> state machines and then it will be compiled into VHDL (even better would be
> into EDIF netlists).
If you build a system that can output VHDL code from Lisp trees, it
shouldn't be too hard to extend it with a Lisp-like macro definition
facility (where the macros are written in Lisp). Once you have that,
extending the language with new syntax is as easy as defining a new
Lisp macro.
Of course, this would give you a language where most of the main
concepts are derived from VHDL. I don't know how hard it would be to
implement an Esterel-like language this way.
An alternative approach would be to build a translator that used the
tree notation as a backend.
Sven-Olof Nystr�m