Duane Rettig wrote:
>
> Any relationship in the G4/G5 names to the Power architectures?
> Or are they really fudging by making their new "360"s out of
> the Power architecture?
My guess is not, since they say that they have multiple execution units
*executing the same instructions* whose results are then compared so
errors can be detected. That doesn't strike me as the sort of thing
you'd do in any kind of consumer processor, although I suppose they
could just be using multiple Power cores or something. Interestingly
they only have 2 execution units (or at least, only two executing the
same instruction stream - presumably each of those units may well have
multiple units for performance reasons), so they can only detect
errors, they can't do some majority-vote thing to carry on even in the
presence of errors. I guess you only need that if you're worried about
radiation / EMP or other really nasty environments.
--tim
···········@tfeb.org" <··········@tfeb.org> writes:
> Interestingly they only have 2 execution units (or at least, only two
> executing the same instruction stream - presumably each of those units
> may well have multiple units for performance reasons), so they can
> only detect errors, they can't do some majority-vote thing to carry on
> even in the presence of errors. I guess you only need that if you're
> worried about radiation / EMP or other really nasty environments.
From what I hear, they simply restart the computation at some earlier,
known-good point on another CPU when they see that one CPU has errors
and mark the bad CPU as such so that it won't be used any more and can
be indicated as needing replacement.
--
Rahul Jain
·····@nyct.net
Professional Software Developer, Amateur Quantum Mechanicist