ASIC DESIGN ENGINEER Agoura Hills CA , Irvine, CA , San Diego, CA
You will be responsible for all phases of ASIC design including definition,
documentation, implementation, simulation, synthesis, timing analysis and
timing closure in physical design for complex ASICs. A background in high
speed ASIC design for data communications, preferably networking specific,
is necessary. Technical skills and knowledge in the following areas are
needed: standard cell /gate array experience, Verilog or VHDL, RTL logic
design and simulation, high-speed design, design for testability, synthesis
and timing analysis. Knowledge of IP, ATM, SONET, TDM and MPLS preferred
but not required. You must be self-motivated and a demonstrated problem
solver. Required: BSEE or equivalent with 4+ years experience and strong
background with industry standard tools from vendors such as Synopsys,
Cadence and IKOS. Knowledge of microprocessor design and data networking
is a plus
·····@nsquare.com
Tel: 909 765 1473