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Parallel Computing: Dataflow Architectures and Languages
(with Programming Laboratory on Monsoon Dataflow Machines)
Monday, August 2 through Friday, August 6, 1993
Massachusetts Institute of Technology
Summer Session Program 6.83s
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Course Abstract
The only thing holding back the widespread use of parallel computers
is software. Most of the difficulty of parallel programming is
attributable to our von Neumann legacy - imperative languages and
sequential processor architectures. By switching to functional
languages, one may start writing parallel programs without even
realizing it. Dataflow architectures further simplify the compilation
problem by providing cheap synchronization.
A central theme of the course is Id, an implicit parallel language.
The participant will get a chance to evaluate via laboratory
experience whether Id is a fad or a real alternative to standard
imperative languages extended for parallelism, such as C with threads,
Multi-Lisp, and Fortran 9X. The participant will also get an
opportunity to compare Id to purely functional languages. Compilation
of Id for both dataflow and von Neumann machines will be discussed at
length.
The other theme of the course is dataflow architectures. We will
discuss why these architectures are better building blocks for
parallel computers than modern RISC architectures. Today's dataflow
architectures borrow much from traditional architectures; however,
they take the most aggressive approach to multi-threading, that is,
rapid context switching to tolerate long memory latencies and frequent
synchronization waits. The participant will get hands-on experience
on Monsoon dataflow machines produced by Motorola, and a chance to
conduct experiments on emulators of other dataflow machines. We will
also discuss several supercomputer-class dataflow machines that are
currently under construction.
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Course Outline:
Implicit Parallel Programming:
Programming with higher-order functions and non-strict data structures;
Rewrite rules and reduction; Algebraic and abstract data types; Arrays
and I-structures; M-structures and non-determinism.
Architectures:
Fundamental issues in high-performance parallel architectures; Static and
dynamic dataflow machines; Split phase memory references; I-structure
memory; Multi-threaded architectures; Hybrid von Neumann-dataflow
architectures.
Compilation:
Dataflow program graphs; Translation to dataflow graphs; Lambda- lifting
and supercombinators; Loop, array and procedure call optimization.
Resource management and performance:
Resource managers; Experimental results on MIT dataflow machines.
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Laboratory:
Morning and afternoon lecture sessions will be followed by late-
afternoon laboratory sessions in writing, debugging, running and
analyzing the performance of Id programs on a Monsoon dataflow machine
and on software emulators. Experienced assistants will be available in
the laboratory.
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The Target Audience:
Understanding dataflow principles can benefit users and designers of all
parallel systems, i.e., parallel languages, architectures, compilers and
resource managers. In addition to computer scientists and electrical
engineers, the course is also useful for people working in scientific
programming, signal processing, real-time computing and artificial
intelligence.
Staff:
The program will be taught by professor Arvind of the MIT Department of
Electrical Engineering and Computer Science.
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FOR MORE INFORMATION:
For a more detailed brochure (including application forms and
information about housing and fees), please contact:
Lori Avirett-Mackenzie
Rm 209
MIT Laboratory for Computer Science
545 Technology Square, Cambridge, MA 02139, USA
ยทยทยทยท@lcs.mit.edu Tel: (617)-253-6837
Fax: (617)-253-6652
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